1. Field of the Invention
This invention relates to a semiconductor device with silicon-film fins and a method of manufacturing the same. More particularly, this invention relates to a MOS (Metal Oxide Semiconductor) transistor with a three-dimensional structure.
2. Description of the Related Art
In recent years, several configurations of a MOS transistor with a three-dimensional structure and several methods of manufacturing such a MOS transistor have been proposed (for example, see E. J. Nowak, et al., “A Functional FinFET-DGCMOS SRAM Cell,” International Electron Device Meeting 2002, pp. 411–414). A MOS transistor with a three-dimensional structure has silicon-film fins functioning as a source and drain. In the MOS transistors with a three-dimensional structure, it is essential to make the width (thickness) of a fin narrower (thinner) than a gate length because of the requirements of transistor characteristics, including to suppress short channel effects.
However, in a MOS transistor with a three-dimensional structure, a fin whose width is narrower than the gate length is difficult to form in such a manner that the fin is prevented from lying down and variance in its garget dimensions are suppressed. In addition to enhance the current driving capability of the transistor, it is necessary to make the fin higher. However, it is very difficult to form a narrow fin with a high aspect ratio in a LSI (Large Scale Integrated circuit).
Furthermore, to form a MOS transistor with a three-dimensional structure, it is necessary to form a stopper layer and a cap layer on the top of the fins in such a process as a CMP (Chemical Mechanical Polishing) process or an RIE (Reactive Ion Etching) process. Since the fins are narrow, the width of the stopper layer and that of the cap layer are also narrow, which decreases process endurance.
Moreover, the width of the gate electrode is also narrow at the top of the narrow fin. Thus, on the top of the fin, the gate electrode cannot directly be contacted with the metal plug which is connected to the first metal layer. Accordingly, the gate electrode needs to be led to a substrate surface and contacted with the metal plug there, leading to a loss in area. Particularly in forming a gate electrode which covers the Si-Fin whose aspect ration is very high, a considerable amount of overetching is required to remove completely the gate polysilicon deposited on the non-gate region. In the overetching, there is a possibility that an undesirable substrate etching will take place or that, if all of the cap layer on the top of the fin has been etched, the fin will be etched as well.
In addition, in a sidewall insulating film (sidewall) formation, it needs to prevent from any interferences to a silicidation of the source and drain. Therefore, the insulating film serving as a sidewall has to be removed completely from the side surface of the fins serving as the source and drain. In this case, a considerable amount of overetching is also required as in the formation of the gate electrode. If the insulating film is left on the side surfaces of the fins, this causes a problem: the silicidation of the source and the drain is non-uniform.